Behavioral “VHDL-AMS” modeling of Single-Electron Transistor

This paper presents a VHDL-AMS model for single-electron transistor (SET) using VHDL-AMS (very high speed descriptive language-analogue and mixed signal). The model is derived from a SPICE macro-model that was designed by Yu´s. The SPICE macro-model was analyzed and simple equations were derived without complicated integrations used to calculate tunnelling rates. These equations define the relation between voltages across and current through the island of an SET. A VHDL-AMS model is designed to describe these equations and the (I-V) characteristics are drawn and compared to the corresponding ones obtained by the SPICE macro-model. In addition, analogue, digital and mixed circuit applications are analyzed to show the validity of the proposed model.