A 400Mb/s Radix-4 MAP Decoder with Fast Recursion Architecture

Turbo decoder´s throughput is highly restricted by the recursion architecture of MAP decoder. In this paper, a new architecture of MAP decoder is presented. We improve the recursion architecture of the traditional radix-4 MAP decoder in order to gain higher throughput, meanwhile the modification could reduce the coding gain loss caused by the approximation of the traditional architecture. A new data flow of the radix-4 MAP decoder is also adopted to reduce the memory access. The proposed architecture could increase the throughput by 21%, while its hardware complexity increase is negligible.