Title :
A near-optimum parallel algorithm for one-dimensional gate assignment problems
Author :
Tsuchiya, Kazuhiro ; Takefuji, Yoshiyasu
Author_Institution :
Dept. of Electr. Eng. & Appl. Phys., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A near-optimum parallel algorithm for one-dimensional gate assignment problems is presented in this paper where the problem is NP-hard. The proposed system is composed of an nn two-dimensional maximum neural network for (n+2)-gate assignment problems. Our algorithm has discovered the improved solution in the benchmark problem over the existing algorithms.
Keywords :
VLSI; computational complexity; integrated circuit design; logic arrays; network routing; neural nets; optimisation; parallel algorithms; 1D gate assignment problems; 2D maximum neural network; NP-hard problem; VLSI layout design; benchmark problem; near-optimum parallel algorithm; Artificial neural networks; Heuristic algorithms; Hysteresis; Logic arrays; NP-complete problem; NP-hard problem; Neural networks; Neurons; Parallel algorithms; Very large scale integration;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.716829
