Modeling of a 14-bit, 100-MS/s pipelined ADC with digital nonlinearity calibration

This paper describes a digital calibration scheme for pipelined analog-to-digital converters (ADCs). The proposed method corrects the nonlinearity caused by finite gain and bandwidth of interstage operational amplifiers as well as the capacitors mismatch in multiplying digital-to-analog converters. The proposed calibration technique takes the advantages of both foreground and background calibration schemes. A behavior simulation is carried out to verify the proposed calibration scheme. Simulation results revealed that for a 14 bit, 100 MS/s pipelined ADC with 0.1% capacitor mismatch, the INL could be limited within ±1.2 LSB and a 76.8 dB SNDR is achieved, due to proposed digital calibration technique.