The Design of Ultra Low Power CMOS CGLNA in Nanometer Technology

In this paper, an ultra low power CMOS common gate LNA (CGLNA) with a capacitive cross-coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the noise figure (NF). In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCCCGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.