Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA

Author

Ghosh, Sudip ; Biswas, Arijit ; Maity, Santi P. ; Rahaman, Hafizur

Author_Institution

Sch. of VLSI Technol., Indian Inst. of Eng. Sci. & Technol.(IIEST), Shibpur, India

fYear

2014

Firstpage

68

Lastpage

72

Abstract

This paper focuses on the design of an improved Discrete Fast Walsh Hadamard Transform (DFWHT) domain digital image watermarking algorithm and its low complexity as well as fast hardware architecture implementation on Xilinx based (version 14.7 Virtex-7 series) FPGA with target device xc7vx1140t-1flg1930, with maximum achieved frequency of 259.202 MHz. The architecture proposed here is to our best knowledge is the first architecture for the corresponding algorithm. Both encoding and extraction algorithm have been verified using MATLAB R2013a. Both gray scale and binary watermarks are used and only gray scale cover image of maximum size (256 × 256) is used. The algorithm and the architecture is applicable for both gray scale and binary watermarks.

Keywords

Hadamard transforms; discrete transforms; encoding; field programmable gate arrays; image watermarking; DFWHT domain; FPGA; MATLAB R2013a; Xilinx version 14.7 Virtex-7 series; binary watermark; digital image watermarking; discrete fast Walsh Hadamard transform; encoding algorithm; extraction algorithm; fast hardware architecture; field programmable gate array; frequency 259.202 MHz; grayscale cover image; xc7vx1140t-1flg1930; Arrays; Decoding; Gray-scale; Radiation detectors; Random access memory; Transforms; Watermarking; DFWHT; Digital Image Watermarking; FPGA; Hardware Architecture; MATLAB; Xilinx;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2014 Fifth International Symposium on

Print_ISBN

978-1-4799-6964-7

Type

conf

DOI

10.1109/ISED.2014.22

Filename

7172749