CA Based Scalable Protocol Processor for Chip Multiprocessors

Author

Dalui, Mamata ; Sikdar, Biplab K.

Author_Institution

Dept. of Comput. Sci. & Eng., Nat. Inst. of Technol., Durgapur, India

fYear

2014

Firstpage

161

Lastpage

165

Abstract

The protocol processor (PP) is a key component of the cache coherence controller (CC) in a Chip Multiprocessors (CMPs) cache system. PP computes the state of a block on every transaction (read/write operation) on the block while maintaining cache coherence in CMPs. This work proposes a novel design approach for the PP which can cater to the pressing need for determining the state of a data block with high accuracy. It is developed around the modelling tool of cellular automata (CA) invented by von Neumann in 1950´s. The inherent regular, modular, cascadable structure of CA ensures high scalability and robustness in exascale design solutions.

Keywords

cache storage; cellular automata; multiprocessing systems; protocols; CA based scalable protocol processor; CC; PP; cache coherence controller; cellular automata; chip multiprocessors cache system; data block; exascale design solutions; Automata; Coherence; Computer architecture; Fault tolerance; Fault tolerant systems; Hardware; Protocols; CMPs; cache coherence; cellular automata; coherence controller; protocol processor;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic System Design (ISED), 2014 Fifth International Symposium on

Print_ISBN

978-1-4799-6964-7

Type

conf

DOI

10.1109/ISED.2014.40

Filename

7172767