FPGA Implementation of Pipelined Blowfish Algorithm

Objective of this paper is to enhance the throughput of Blowfish block cipher by designing a pipelined architecture of the same followed by implementation and evaluation of its performance in Field Programmable Gate Array. The proposed architecture was implemented by using Verilog HDL and was synthesized, placed and routed in Spartan3E chip XC3s500e-5fg320 using ISE Design Suite 12.1. Performance analysis of the proposed pipelined design shows a throughput of 6.3 Gbps as compared to 588.255 Mbps for non-pipelined design.