A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC

This paper instigates a "design of an 8-bit Asynchronous-Successive Approximation Register (ASAR) ADC (analog-to-digital converter) employing a Charge Scaling DAC (digital-to-analog converter)". The design itemizes the word asynchronous, which claims it to be independent of the external clock signal. The proposed design is composed of a Comparator, Charge Scaling DAC and a digital SAR logic block. The design was simulated using 180nm CMOS technology and operated on a single 1 V power supply which dissipated a power of 32.419μW which is much lesser compared to the other existing architecture such as current scaling DAC and voltage scaling DAC.