Title :
Analysis of local interconnect resistance at scaled process nodes
Author :
Pandey, R. ; Agrawal, N. ; Arghavani, R. ; Datta, S.
Author_Institution :
Pennsylvania State Univ., University Park, PA, USA
Abstract :
A detailed analysis of local interconnect resistance with process scaling to 5 nm technology node is presented for both SD and DD interconnects. W M0 and Contact are identified as key resistance contributors at 5 nm process. Introducing a lower resistivity W for metal fill in M0 and Contact shows 43% reduction in M0/M1 resistance along with 5% gain in ION which are significant for ultra-low Vcc based 5 nm process.
Keywords :
integrated circuit interconnections; dual damascene interconnect; local interconnect resistance; scaled process nodes; single damascene interconnect; size 5 nm; Conductivity; Current density; Logic gates; Resistance; Three-dimensional displays; Tin;
Conference_Titel :
Device Research Conference (DRC), 2015 73rd Annual
Print_ISBN :
978-1-4673-8134-5
DOI :
10.1109/DRC.2015.7175620
