Analysis of local interconnect resistance at scaled process nodes

A detailed analysis of local interconnect resistance with process scaling to 5 nm technology node is presented for both SD and DD interconnects. W M0 and Contact are identified as key resistance contributors at 5 nm process. Introducing a lower resistivity W for metal fill in M0 and Contact shows 43% reduction in M0/M1 resistance along with 5% gain in I_ON which are significant for ultra-low V_cc based 5 nm process.