Yield enhancement challenges for 90 nm and beyond

Author

Goel, Honey ; Dance, Daren

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2003

Firstpage

262

Lastpage

265

Abstract

This paper highlights that some processing issues, which typically are systematic in nature, could cause random effects due to marginality issues. High aspect ratio structures, such as contacts and via challenges are exacerbated due to high density, increased critical area, and detection limitations. Process complexity, defect free mask production, and wafer handling issues also add to the challenge of ramping yields quickly.

Keywords

VLSI; chemical mechanical polishing; integrated circuit interconnections; integrated circuit yield; materials handling; nanotechnology; 90 nm; ITRS; contact defects; defect free mask production; high aspect ratio structures; process complexity; processing issues; random defects; systematic defects; via defects; wafer handling issues; yield enhancement; Acceleration; Control systems; Delay; Fault detection; Implants; Inspection; Production; Semiconductor device manufacture; Semiconductor device modeling; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference and Workshop, 2003 IEEEI/SEMI

ISSN

1078-8743

Print_ISBN

0-7803-7681-1

Type

conf

DOI

10.1109/ASMC.2003.1194504

Filename

1194504

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3599836