Hardware/software co-simulation methodology based on two alternative approaches

This paper presents two co-simulation techniques for mixed hardware/software systems. The first technique is best suited for functional verification, while the second one is best suited for performance evaluation. In the first technique, the software part is executed on the host processor and communicates with the hardware part through the use of text files and a VHDL functional model of the μP bus incorporated in the system. The second technique is based on an efficient, in terms of speed, VHDL model of a generic instruction-set-simulator that executes the software part and on a functional model of the particular μP bus, similarly to the first technique. Both techniques have been practiced in real developments. Both techniques are presented in detail along with development issues and trade-offs. The two methods are evaluated and compared, based on data acquired from real developments of hardware/software systems