Title :
Design guidelines to achieve a very high ESD robustness in a self-biased NPN
Author :
Tremouilles, David ; Bertrand, Geraldine ; Bafleur, Marise ; Nolhier, Nicolas ; Lescouzeres, Lionel
Author_Institution :
LAAS-CNRS, 7 av. du Colonel Roche - 31077 TOULOUSE Cedex 4-France
Abstract :
In this paper, using extensive TCAD simulations and measurement results, we analyze the basic mechanisms involved during an ESD stress in a self-biased NPN bipolar transistor used as an ESD protection. From the deep understanding of these mechanisms, we define design guidelines to achieve a very high ESD robustness (=10kV) in this type of device. These guidelines are validated on several CMOS technologies.
Keywords :
Analytical models; Bipolar transistors; CMOS technology; Electrostatic discharge; Failure analysis; Guidelines; Protection; Robustness; Stress measurement; Voltage;
Conference_Titel :
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Print_ISBN :
978-1-5853-7040-5
Electronic_ISBN :
978-1-5853-7040-5
