Improved structures for power MOSFETs with on-chip full protection

Power MOSFETs with built-in shorted load protection have been recently presented where a lateral npn transistor pulls down the gate to limit the drain current, but a parasitic vertical npn can limit the operating voltage below the power MOSFET´s BV_DSS. Further structural modifications so far devised result in large power losses or strongly non-linear characteristics. Such drawbacks have been overcome by a new LNPN structure, or by an NMOSFET, whose performance are optimized with a dedicated implant. The devices with bipolar-based feedback network exhibit better limiting behaviour, but similar performance can be achieved by increasing the sense ratio in the NMOSFET-based devices. All the devices feature ESD protection and an active gate-drain clamp to enhance ruggedness. The clamping voltage is set below the power MOSFET´s BV_DSS, is independent of the epilayer parameters, and has a low temperature coefficient, thus resulting in very predictable performance