Title :
Architectural Reliability: Lifetime Reliability Characterization and Management ofMany-Core Processors
Author :
Song, William ; Mukhopadhyay, Saibal ; Yalamanchili, Sudhakar
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
This paper presents a lifetime reliability characterization of many-core processors based on a full-system simulation of integrated microarchitecture, power, thermal, and reliability models. Under normal operating conditions, our model and analysis reveal that the mean-time-to-failure of cores on the die show normal distribution. From the processor-level perspective, the key insight is that reducing the variance of the distribution can improve lifetime reliability by avoiding early failures. Based on this understanding, we present two variance reduction techniques for proactive reliability management; i) proportional dynamic voltage-frequency scaling (DVFS) and ii) coordinated thread swapping. A major advantage of using variance reduction techniques is that the improvement of system lifetime reliability can be achieved without adding design margins or spare components.
Keywords :
integrated circuit design; microprocessor chips; multiprocessing systems; power aware computing; DVFS; architectural reliability; coordinated thread swapping; core mean-time-to-failure; design margins; full-system simulation; integrated microarchitecture; lifetime reliability characterization; many-core processors; normal operating conditions; power models; proportional dynamic voltage-frequency scaling; reliability models; spare components; thermal models; variance reduction techniques; Benchmark testing; Degradation; Gaussian distribution; Integrated circuit reliability; Microarchitecture; Program processors; Computer architecture, lifetime estimation, modeling, semiconductor device reliability, simulation;
Journal_Title :
Computer Architecture Letters
DOI :
10.1109/LCA.2014.2340873