• DocumentCode
    3600703
  • Title

    Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision

  • Author

    Bo Yuan ; Parhi, Keshab K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
  • Volume
    23
  • Issue
    10
  • fYear
    2015
  • Firstpage
    2268
  • Lastpage
    2280
  • Abstract
    Polar codes, as the first provable capacity-achieving error-correcting codes, have received much attention in recent years. However, the decoding performance of polar codes with traditional successive-cancellation (SC) algorithm cannot match that of the low-density parity-check or Turbo codes. Because SC list (SCL) decoding algorithm can significantly improve the error-correcting performance of polar codes, design of SCL decoders is important for polar codes to be deployed in practical applications. However, because the prior latency reduction approaches for SC decoders are not applicable for SCL decoders, these list decoders suffer from the long-latency bottleneck. In this paper, we propose a multibit-decision approach that can significantly reduce latency of SCL decoders. First, we present a reformulated SCL algorithm that can perform intermediate decoding of 2 b together. The proposed approach, referred as 2-bit reformulated SCL (2b-rSCL) algorithm, can reduce the latency of SCL decoder from (3n-2) to (2n-2) clock cycles without any performance loss. Then, we extend the idea of 2-b-decision to general case, and propose a general decoding scheme that can perform intermediate decoding of any 2K bits simultaneously. This general approach, referred as 2K-bit reformulated SCL (2K b-rSCL) algorithm, can reduce the overall decoding latency to as short as n/2K-2-2 cycles. Furthermore, on the basis of the proposed algorithms, very large-scale integration architectures for 2b-rSCL and 4b-rSCL decoders are synthesized. Compared with a prior SCL decoder, the proposed (1024, 512) 2b-rSCL and 4b-rSCL decoders can achieve 21% and 60% reduction in latency, 1.66 and 2.77 times increase in coded throughput with list size 2, and 2.11 and 3.23 times increase in coded throughput with list size 4, respectively.
  • Keywords
    VLSI; decoding; error correction codes; parity check codes; turbo codes; 2-bit reformulated SCL algorithm; 2b-rSCL algorithm; 2b-rSCL decoders; 2n-2 clock cycles; 3n-2 clock cycles; 4b-rSCL decoders; SC list decoding algorithm; SCL decoder design; capacity-achieving error-correcting codes; error-correcting performance improvement; intermediate decoding; latency reduction; long-latency bottleneck; low-density parity-check codes; low-latency successive-cancellation list decoders; multibit decision; polar codes; successive-cancellation algorithm; turbo codes; very large-scale integration architectures; Algorithm design and analysis; Clocks; Computer architecture; Decoding; Sorting; Very large scale integration; Algorithm reformulation; list decoding; multibit decision; polar codes; successive cancellation (SC); successive cancellation (SC).;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2359793
  • Filename
    6920050