Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP

The combination of software flexibility and hardware configurability makes partially reconfigurable application-specific instruction-set processor (rASIP) an attractive architecture, which matches the needs of computation-intensive and fast-evolving wireless receiver algorithms. This paper describes the design of a multimode multiple-input-multiple-output (MIMO) detector by using rASIP, which supports multiple MIMO detection algorithms with different antenna and modulation configurations. The rASIP is mainly constructed using a coarse-grained reconfigurable architecture (CGRA) coupled with a processor. In MIMO detection, some important computation steps (e.g., preprocessing) or even the whole detection algorithm is realized using matrix operations. Therefore, for the rASIP, the CGRA is designed to efficiently support different matrix operations used in MIMO detection, and the processor is integrated with special instructions to implement the control path required by different algorithms. Feasibility of the proposed approach is shown by implementing three noniterative MIMO detection algorithms. To evaluate the flexibility of the proposed approach, a Markov Chain Monte Carlo based MIMO detection is also realized by mapping part of the algorithm by using matrix operations on the CGRA. Postlayout results of the rASIP are generated for the implemented detection algorithms on a 65-nm CMOS technology. Compared with some selected designs based on programmable architectures and dedicated application-specified integrated circuits (ASICs), we show that following the proposed approach, the rASIP-based multimode MIMO detection, is about 1.6-5.4 times more efficient than the programmable architectures, and it approaches the throughput performance to the dedicated ASICs.