• DocumentCode
    3600739
  • Title

    Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems

  • Author

    Jing-Shiun Lin ; Yin-Tsung Hwang ; Shih-Hao Fang ; Po-Han Chu ; Ming-Der Shieh

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • Volume
    23
  • Issue
    10
  • fYear
    2015
  • Firstpage
    2342
  • Lastpage
    2346
  • Abstract
    QR decomposition is a fundamental operation widely used in various signal detection schemes for multiple-input multiple-output (MIMO) systems. In this brief, a high-throughput converted form QR factorization (QRF) is investigated. The proposed two-phase computing scheme starts with a direct form factorization followed by a postprocessing using simple row/column permutations. Using coordinate rotation digital computer (CORDIC) algorithm, a massively parallel array architecture consisting of pipelined and folded CORDIC modules is developed to enhance the throughput. In addition, chaining mode operation is supported, where five successive signal vector updates can be performed the following every factorization. The chip implementation result in TSMC 0.18-μm CMOS process indicates the design, with an equivalent gate count 192100, can operate at 200 MHz and accomplish 25-M complex-valued QRF per second. This suggests a highest 3-Gb/s data rate for signal detections in a 4 × 4 MIMO system. The proposed design also outperforms other designs in two compound performance indices, i.e., data rate normalized with respect to gate count and power consumption, respectively.
  • Keywords
    CMOS integrated circuits; MIMO communication; parallel architectures; pipeline arithmetic; radio receivers; signal detection; singular value decomposition; MIMO system; QR factorization; QRF; TSMC CMOS process; bit rate 3 Gbit/s; chaining mode operation; coordinate rotation digital computer; equivalent gate count; folded CORDIC module; frequency 200 MHz; low complexity high-throughput QR decomposition design; massively parallel array architecture; multiple input multiple output; pipeline CORDIC module; power consumption; row-column permutation; signal detection scheme; size 0.18 mum; throughput enhancement; two-phase computing scheme; Clocks; Complexity theory; Hardware; Logic gates; MIMO; Matrix converters; Vectors; Coordinate rotation digital computer (CORDIC); QR decomposition (QRD); QR decomposition (QRD).; multiple-input–multiple-output (MIMO); multiple-input???multiple-output (MIMO);
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2014.2361906
  • Filename
    6936368