Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation

When operating at scaled supply voltages, the primary source of performance degradation in a successive approximation register (SAR) analog-to-digital converter (ADC) is the comparator thermal noise. Low-noise comparator can be used but at the expense of increased power dissipation. This paper presents an approach to reduce the comparator power in SAR ADCs. A mathematical model of a SAR ADC derived in this paper suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary. A noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step. As a proof of concept, a 10-bit SAR ADC that operates at 0.5-V supply voltage and supports a flexible differential input dynamic range from 0.4 to 1 V has been fabricated in 65-nm CMOS process. The prototype achieves an effective number of bits ranging from 7.1 to 9.1 bits and a figure of merit from 3.3 to 6.8 fJ/conversion step while operating at 250 kS/s.