DocumentCode :
3600858
Title :
Sequential Element Timing Parameter Definition Considering Clock Uncertainty
Author :
Harris, David Money
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Volume :
23
Issue :
11
fYear :
2015
Firstpage :
2705
Lastpage :
2708
Abstract :
When the conventional method of defining sequential element timing parameters is used in conjunction with the conventional method of accounting for clock uncertainty in timing analysis, the results are overly pessimistic because, when clock uncertainty is nonzero, the element can never be simultaneously critical for both setup time and clock-toQ. This brief shows that the actual sequencing overhead of conventional flip-flops is 0.5-1 fanout-of-4 (FO4) inverter delay shorter than conventional models predict. High-performance flip-flops, with a modest transparency window, can be 2 FO4 delays faster. While the exact overhead becomes a function of the clock uncertainty, for typical uncertainties, the timing parameters are well-approximated using minimum setup and clock-toQ values.
Keywords :
clocks; flip-flops; sequential circuits; timing circuits; FO4 inverter delay; clock uncertainty; clock-to-Q; fanout-of-4; flip-flop; sequencing overhead; sequential element timing parameter definition; Clocks; Delays; Latches; Sequential analysis; Uncertainty; Very large scale integration; Clock skew; flip-flops; timing analysis; timing analysis.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2364991
Filename :
6964789
Link To Document :
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