A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

A system clock with a 50% duty cycle is demanded in high-speed data communication applications, such as double data rate memories and double sampling analog-to-digital converters. In this paper, a wide-range low-cost all-digital duty-cycle corrector (ADDCC) is presented. The proposed ADDCC uses a delay-recycled half-cycle time delay line to reduce the required length of the delay line to half of the input clock period. Thus, it can extend the operating frequency toward a lower frequency with small area cost as compared with the conventional design. The proposed design is implemented in a standard performance 90-nm CMOS process, and the active area is 170 × 170 μm². The input frequency of the proposed ADDCC ranges from 75 to 734 MHz, and the input duty-cycle ranges from 9% to 86%. The measured output duty-cycle error is less than 1.78%. The proposed ADDCC consumes 4.59 mW at 734 MHz and 0.9 mW at 75 MHz with a 1.0-V power supply.