Title :
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages
Author :
Lacruz, Jesus O. ; Garcia-Herrero, Francisco ; Valls, Javier
Author_Institution :
Dept. of Electr. Eng., Univ. de Los Andes, Merida, Venezuela
Abstract :
In this brief, a method for compressing the messages between check nodes and variable nodes is proposed. This method is named compressed nonbinary message passing (CNBMP). CNBMP reduces the number of messages exchanged between one check node and the connected variable nodes from dc x q to 5 × q, and its application has a high impact on the performance of the decoder: the storage and routing areas are reduced and the throughput is increased. Unlike other methods, CNBMP does not introduce any approximation or modification in the information and the processed operations are exactly the same as those of the original decoders; hence, no performance degradation is introduced. To demonstrate its advantages, an architecture applying this CNBMP to the Trellis Min-Max algorithm was derived showing that most of the storage resources were also reduced from dc × q to 5 × q. This architecture was implemented for a (837 726) nonbinary low-density parity-check code using a 90-nm CMOS technology reaching a throughput of 981 Mb/s with an area of 10.67 mm2, which is 3.9 more efficient than the best solution found in the literature.
Keywords :
CMOS integrated circuits; data compression; message passing; minimax techniques; parity check codes; trellis codes; CMOS technology; CNBMP; check nodes; compressed nonbinary message passing; nonbinary LDPC decoders; nonbinary low-density parity-check code; omplexity reduction; trellis min-max algorithm; variable nodes; Computer architecture; Decoding; Hardware; Logic gates; Parity check codes; Reliability; Throughput; Decoding; LDPC codes; hardware implementation; high throughput; nonbinary (NB); nonbinary (NB).;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2014.2377194