DocumentCode :
3601130
Title :
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks
Author :
Pomeranz, Irith
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
23
Issue :
12
fYear :
2015
Firstpage :
3006
Lastpage :
3014
Abstract :
This paper describes a test compaction procedure that considers a set of functional test sequences for a set of logic blocks in a design. The logic blocks may have different numbers of primary inputs, and functional test sequences of different lengths. The procedure expands the test sequences such that every sequence is applicable to every logic block. It then concatenates and compacts the sequences into a single sequence. In this process, it considers the logic blocks one at a time to avoid the need to store and simulate all the logic blocks simultaneously. The resulting test sequence can be applied to all the logic blocks in parallel. The experimental results demonstrate the levels of test compaction that can be achieved by this approach. The results also demonstrate that the resulting sequence has an improved coverage of faults that were not targeted during the generation of the functional test sequences or the test compaction procedure.
Keywords :
logic circuits; logic testing; functional test sequences; logic blocks; test compaction; Bismuth; Circuit faults; Clocks; Compaction; Computational complexity; Computational modeling; Vectors; Finite-state machines; functional test sequences; test compaction; test data volume; test data volume.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2382609
Filename :
7006798
Link To Document :
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