DocumentCode
3601153
Title
Design and Low-Complexity Implementation of Matrix-Vector Multiplier for Iterative Methods in Communication Systems
Author
Alshawi, Tariq ; Bentrcia, Abdelouahab ; Alshebeili, Saleh
Author_Institution
Dept. of Electr. Eng., King Saud Univ., Riyadh, Saudi Arabia
Volume
23
Issue
12
fYear
2015
Firstpage
3099
Lastpage
3103
Abstract
Iterative methods are basic building blocks of communication systems and often represent a dominating part of the system, and therefore, they necessitate careful design and implementation for optimal performance. In this brief, we propose a novel field programmable gate arrays design of matrix-vector multiplier that can be used to efficiently implement widely adopted iterative methods. The proposed design exploits the sparse structure of the matrix as well as the fact that spreading code matrices have equal magnitude entries. Implementation details and timing analysis results are promising and are shown to satisfy most modern communication system requirements.
Keywords
field programmable gate arrays; iterative methods; matrix algebra; communication system requirements; communication systems; field programmable gate arrays design; iterative methods; low complexity implementation; magnitude entries; matrix vector multiplier; optimal performance; spreading code matrices; timing analysis; Adders; Delays; Field programmable gate arrays; Hardware; Iterative methods; Multiaccess communication; Sparse matrices; Field programmable gate array (FPGA); multiple access; nonmonotone line search; parallel interference cancellation; real time; real time.;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2014.2387476
Filename
7010047
Link To Document