Design and Implementation of Time and Frequency Synchronization in LTE

A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we propose the sign-bit maximum-likelihood sequence detection algorithm for the secondary synchronization signal analysis. These methods result in 90% hardware reduction in the cell search compared with the state-of-the-art design. Moreover, possible structures for the frequency tracking in LTE are investigated leading to an experimental comparison, used to choose the best hardware-efficient structure. The proposed architecture is fabricated in a 130-nm CMOS technology occupying 0.68 mm² of silicon area. At 25 °C and 1.2 V supply voltage, the fabricated chip consumes 34.4 mW at 42 MHz in the time domain and 34.6 mW at 188 MHz in the frequency domain. The fabricated and tested synchronizer core proves to have an outstanding performance for all defined communication modes in LTE.