• DocumentCode
    3601262
  • Title

    Real-Time High-Quality Stereo Vision System in FPGA

  • Author

    Wenqiang Wang ; Jing Yan ; Ningyi Xu ; Yu Wang ; Feng-Hsiung Hsu

  • Author_Institution
    Microsoft Res. Asia, Beijing, China
  • Volume
    25
  • Issue
    10
  • fYear
    2015
  • Firstpage
    1696
  • Lastpage
    1708
  • Abstract
    Stereo vision is a well-known technique for acquiring depth information. In this paper, we propose a real-time high-quality stereo vision system in field-programmable gate array (FPGA). Using absolute difference-census cost initialization, cross-based cost aggregation, and semiglobal optimization, the system provides high-quality depth results for high-definition images. This is the first complete real-time hardware system that supports both cost aggregation on variable support regions and semiglobal optimization in FPGAs. Furthermore, the system is designed to be scaled with image resolution, disparity range, and parallelism degree for maximum parallel efficiency. We present the depth map quality on the Middlebury benchmark and some real-world scenarios with different image resolutions. The results show that our system performs the best among FPGA-based stereo vision systems and its accuracy is comparable with those of current top-performing software implementations. The first version of the system was demonstrated on an Altera Stratix-IV FPGA board, processing 1024 × 768 pixel images with 96 disparity levels at 67 frames/s. The system is then scaled up on a new Altera Stratix-V FPGA and the processing ability is enhanced to 1600 × 1200 pixel images with 128 disparity levels at 42 frames/s.
  • Keywords
    field programmable gate arrays; optimisation; stereo image processing; Altera Stratix-IV FPGA board; FPGA; Middlebury benchmark; absolute difference-census cost initialization; cross-based cost aggregation; field-programmable gate array; high-definition images; maximum parallel efficiency; real-time high-quality stereo vision system; semiglobal optimization; Accuracy; Field programmable gate arrays; Hardware; Optimization; Parallel processing; Real-time systems; Stereo vision; FPGA; Field-programmable gate array (FPGA); High-quality depth map; Stereo vision; hardware accelerator; high-quality depth map; stereo vision;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems for Video Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1051-8215
  • Type

    jour

  • DOI
    10.1109/TCSVT.2015.2397196
  • Filename
    7027849