DocumentCode :
3601264
Title :
Traffic-Based Virtual Channel Activation for Low-Power NoC
Author :
Muhammad, Sayed Taha ; Ezz-Eldin, Rabab ; El-Moursy, Magdy A. ; El-Moursy, Ali A. ; Refaat, Amr M.
Author_Institution :
Dept. of Electr. Eng., Beni-Suef Univ., Beni-Suef, Egypt
Volume :
23
Issue :
12
fYear :
2015
Firstpage :
3029
Lastpage :
3042
Abstract :
A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <;2% degradation in throughput. The implementation overhead of TVA is negligible.
Keywords :
logic design; low-power electronics; multiplexing; network-on-chip; power consumption; semiconductor switches; virtualisation; 2D-mesh NoC; 2D-torus NoC; NoC switch; NoC throughput; TVA algorithm; adaptive virtual channel technique; hierarchical multiplexing tree; high-leakage power saving; leakage power consumption; low-leakage power switch; low-power NoC; network average leakage power; network-on-chip; power dissipation; power reduction techniques; power supply gating; throughput degradation; traffic-based virtual channel activation; Ports (Computers); Power dissipation; Switches; Switching circuits; System-on-chip; Throughput; Transistors; Adaptive virtual channel (AVC); high throughput; leakage power reduction; network-on-chip (NoC); power gating (PG); system-on-chip (SoC); system-on-chip (SoC).;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2387797
Filename :
7027854
Link To Document :
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