Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization

In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching.