Design of Schmitt Trigger Logic Gates Using DTMOS for Enhanced Electromagnetic Immunity of Subthreshold Circuits

This paper presents subthreshold digital circuit design and optimization method using Schmitt trigger logic gates for enhanced electromagnetic immunity. The proposed Schmitt trigger logic gates are based on a buffer design using dynamic threshold-voltage MOS for low-power operation. By expanding the Schmitt trigger to NAND/NOR gate, we can dramatically improve the noise immunity with much lower switching power consumption and significant area reduction compared with CMOS Schmitt triggers, at the expense of a slight increase in delay. Not only for the gate level, but also the circuit level immunity improvement is verified with ISCAS 85 benchmark. In addition, we propose a parameter to determine the optimal noise immunity considering the tradeoff between immunity and performance. By using the proposed parameter, optimal hysteresis can be chosen for the reasonable performance deterioration.