Transistor-Less Spin Torque Transfer Magnetic Random Access Memory Cell Design

Current mainstream spin torque transfer magnetic random accessible memory (STT-MRAM) architecture requires an isolation transistor in each MRAM cell. Processing flow for magnetic tunneling junctions is intrinsically capable of multilayer 3-D integration. However, there is no mature multilayer 3-D CMOS technology available. Therefore, including isolation CMOS transistor in each MRAM cell makes it impractical to achieve a 3-D multilayer MRAM. In this paper, we investigate the feasibility of a new transistor-less MRAM architecture aiming for multilayer 3-D STT-MRAM. In addition to a new array structure, new programming and reading mechanisms are presented. Various voltage biasing schemes are introduced to address individual bits during writing and reading operations. The first-order feasibility is demonstrated by analysis and numerical simulation on programming current margin.