Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias

3-D integrated circuits (3-D ICs) make use of the vertical dimension for smaller footprint, higher speed, lower power consumption, and better timing performance. In 3-D ICs, the inter-tier-via (ITV) is a critical enabling technique because it forms vertical signal and power paths. Accordingly, it is imperative to accurately and efficiently extract the electrostatic capacitances of ITVs using field solvers. Unfortunately, the cylindrical via shape presents major challenges to most of the existing methods. To address this issue, we develop a novel floating random walk (FRW) method by rotating the transition cube to suit the cylindrical surface, devising a special space management technique, and proposing accelerating techniques for structures with large-sized through-silicon-vias. Experiments on typical ITV structures suggest that the proposed techniques is up to hundreds times faster than a simple FRW approach and the boundary element method-based algorithms, without loss of accuracy. In addition, compared with extracting the square-approximation structures, the proposed techniques can reduce the error by 10×. Large and multidielectric structures have also been tested to demonstrate the versatility of the proposed techniques.