Title :
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider
Author :
Kai-Hui Zeng ; Ting-Kuei Kuan ; Shen-Iuan Liu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A subharmonically injection-locked all-digital phaselocked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without a time-todigital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process; it consumes 3.04 mW under a standard supply of 1.1 V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4 dBc/Hz at 1-MHz offset. The integrated RMS jitter is 109.6 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure-of-merit is equal to -254.39 dB.
Keywords :
CMOS integrated circuits; digital phase locked loops; phase noise; CMOS process; PVT variations; frequency locking; injection pulse; integrated RMS jitter; phase locked loop; phase locking; phase noise; power 3.04 mW; process-voltage-temperature variations; simple bang-bang phase detector; size 40 nm; subharmonically injection-locked all-digital PLL; time 109.6 fs; voltage 1.1 V; Harmonic analysis; Jitter; Phase locked loops; Phase noise; Temperature measurement; Timing; Varactors; All-digital phase-locked loop (ADPLL); all-digital phase-locked loop; injection locked; injection-locked; sub-harmonically; subharmonically;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2015.2455292