DocumentCode :
3603894
Title :
A Continuous-Time 
ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation
Author :
Yue Hu ; Venkatram, Hariprasath ; Maghari, Nima ; Un-Ku Moon
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
Volume :
62
Issue :
11
fYear :
2015
Firstpage :
1063
Lastpage :
1067
Abstract :
This brief presents a 120-MS/s continuous-time delta-sigma analog-to-digital conversion with a dual-slope-based time-interleaved quantizer in a 0.18-μm complementary metal- oxide-semiconductor process. Excess loop delay of two sample clocks is compensated using the time information made available through interleaved channel coupling. As a result, one full clock cycle is afforded to digital-to-analog conversion dynamic element matching (DEM) operation, allowing for a digitally synthesized DEM block.
Keywords :
CMOS integrated circuits; clocks; delta-sigma modulation; quantisation (signal); complementary metal oxide semiconductor process; continuous-time ΔΣ ADC; delta-sigma analog-to-digital conversion; digital-to-analog conversion; digitally synthesized DEM block; dual-slope-based time-interleaved quantizer; dynamic element matching; excess loop delay compensation; interleaved channel coupling; size 0.18 mum; time information; two sample clocks; Circuits and systems; Clocks; Couplings; Delays; Frequency measurement; Modulation; Moon; Analog-to-digital conversion (ADC); CMOS analog integrated circuits; complementary metal???oxide???semiconductor (CMOS) analog integrated circuits; delta-sigma $(Delta Sigma)$ modulation; delta-sigma modulation; excess loop delay (ELD) compensation; excess loop delay compensation;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2015.2457011
Filename :
7163556
Link To Document :
