An Optimum Architecture for Continuous-Flow Parallel Bit Reversal

With the aim of minimizing memory and latency, this letter presents a novel bit-reversal architecture for continuous-flow parallel pipelined FFT processors. It harnesses the theory that any permutation can be decomposed to a series of elementary bit-exchanges. The main contribution of this letter are twofold. First, it achieves continuous-flow bit reversal in parallel with the minimum memory and minimum latency. Second, the architecture, composed of memory and 2-to-1 multiplexers, are simple and regular for general power-of-2 parallelism. Furthermore, it supports different common radices, including radix-2,radix-4, and radix-8.