Modeling and Characterization of the Abnormal Hump in n-Channel Amorphous-InGaZnO Thin-Film Transistors After High Positive Bias Stress

Hump characteristics of n-channel amorphous indium-gallium-zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage (V_T) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS (V_GS = 30, V_DS = 30; V_GD = V_GS - V_DS = 0 V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage (V_Tp) and a shorter effective channel length (L_chp ≅ Lov) compared with those (V_Tm and L_ch) of the main TFT.