DocumentCode :
3605081
Title :
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Author :
Akopyan, Filipp ; Sawada, Jun ; Cassidy, Andrew ; Alvarez-Icaza, Rodrigo ; Arthur, John ; Merolla, Paul ; Imam, Nabil ; Nakamura, Yutaka ; Datta, Pallab ; Gi-Joon Nam ; Taba, Brian ; Beakes, Michael ; Brezzo, Bernard ; Kuang, Jente B. ; Manohar, Rajit ; R
Author_Institution :
IBM Res. - Almaden, San Jose, CA, USA
Volume :
34
Issue :
10
fYear :
2015
Firstpage :
1537
Lastpage :
1557
Abstract :
The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation, low-power consumption and scalability, which require a radical departure from conventional system design. Brain-inspired architectures offer tremendous promise in this area. To this end, we developed TrueNorth, a 65 mW real-time neurosynaptic processor that implements a non-von Neumann, low-power, highly-parallel, scalable, and defect-tolerant architecture. With 4096 neurosynaptic cores, the TrueNorth chip contains 1 million digital neurons and 256 million synapses tightly interconnected by an event-driven routing infrastructure. The fully digital 5.4 billion transistor implementation leverages existing CMOS scaling trends, while ensuring one-to-one correspondence between hardware and software. With such aggressive design metrics and the TrueNorth architecture breaking path with prevailing architectures, it is clear that conventional computer-aided design (CAD) tools could not be used for the design. As a result, we developed a novel design methodology that includes mixed asynchronous-synchronous circuits and a complete tool flow for building an event-driven, low-power neurosynaptic chip. The TrueNorth chip is fully configurable in terms of connectivity and neural parameters to allow custom configurations for a wide range of cognitive and sensory perception applications. To reduce the system´s communication energy, we have adapted existing application-agnostic very large-scale integration CAD placement tools for mapping logical neural networks to the physical neurosynaptic core locations on the TrueNorth chips. With that, we have successfully demonstrated the use of TrueNorth-based systems in multiple applications, including visual object recognition, with higher performance and orders of magnitude lower power consumpt- on than the same algorithms run on von Neumann architectures. The TrueNorth chip and its tool flow serve as building blocks for future cognitive systems, and give designers an opportunity to develop novel brain-inspired architectures and systems based on the knowledge obtained from this paper.
Keywords :
CMOS digital integrated circuits; low-power electronics; real-time systems; CAD tools; CMOS scaling trends; TrueNorth; TrueNorth architecture; asynchronous-synchronous circuits; cognitive perception applications; conventional computer-aided design tools; defect-tolerant architec- ture; event-driven routing infrastructure; intelligent computing; large-scale integration CAD placement; low-power architecture; low-power consumption; neuron programmable neurosynaptic chip; noisy multisensory data; non-von Neumann architecture; power 65 mW; real-time operation; sensory perception applications; Architecture; Biological neural networks; Computer architecture; Nerve fibers; Real-time systems; Synchronization; Asynchronous circuits; asynchronous communication; design automation; design methodology; image recognition; logic design; low-power electronics; neural network hardware; neural networks; neuromorphics; parallel architectures; real-time systems; synchronous circuits; very large-scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2015.2474396
Filename :
7229264
Link To Document :
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