• DocumentCode
    3605517
  • Title

    Correction to “A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS” [Jul 15 1722-1735]

  • Author

    Shahramian, Shayan ; Chan Carusone, Anthony

  • Author_Institution
    Department of Electrical & Computer Engineering, University of Toronto, Toronto, ON, Canada
  • Volume
    50
  • Issue
    10
  • fYear
    2015
  • Firstpage
    2463
  • Lastpage
    2463
  • Abstract
    Presents corrections to the paper, ???A 0.41 pJ/bit 10 Gb/s hybrid 2 IIR and 1 discrete-time DFE tap in 28 nm-LP CMOS,??? (Shahramian, S.) IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1722???1735, Jul. 2015.
  • Keywords
    CMOS integrated circuits; Decision feedback equalizers; Intersymbol interference;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2015.2470855
  • Filename
    7244263
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3605517