Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

Author

Gupta, Ankur ; Shrivastava, Mayank ; Baghini, Maryam Shojaei ; Sharma, Dinesh Kumar ; Gossner, Harald ; Rao, V. Ramgopal

Author_Institution

Dept. of Electr. Eng., IIT Bombay, Mumbai, India

Volume

62

Issue

10

fYear

2015

Firstpage

3168

Lastpage

3175

Abstract

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in RON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Keywords

CMOS integrated circuits; MIS devices; MOSFET; semiconductor device models; technology CAD (electronics); time-domain analysis; RF performance; RF power applications; advanced CMOS technology; drain-extended MOS transistor; frequency 1 GHz; high-voltage MOS device; large-signal time-domain analysis; shallow trench isolation; static performance; well-calibrated TCAD simulations; CMOS integrated circuits; Capacitance; Logic gates; Optimization; Performance evaluation; Radio frequency; Standards; Advanced CMOS; drain-extended MOS (DeMOS); high-power RF; integrated RF power amplifier (PA); system-on-chip (SoC); system-on-chip (SoC).;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2015.2470117

Filename

7247702