Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented.