Characterization of Single-Event Transient Pulse Quenching among Dummy Gate Isolated Logic Nodes in 65 nm Twin-Well and Triple-Well CMOS Technologies

As chip technologies scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes. The so-called pulse quenching effect, induced by single-event charge sharing collection, has been widely explored in efforts to find mitigation techniques for single-event transients (SETs) or single-event upsets (SEUs), and the dummy gate isolation has been proven to be an efficient layout technique for pulse quenching enhancement. In this paper, the characterization of SET pulse quenching among dummy gate isolated logic nodes is performed in 65 nm twin-well and triple-well CMOS technologies. Four groups of heavy ion experiments are explored for the characterization, and the pulse quenching effect is quantitatively analyzed in detail. The pulse quenching effects show different characteristics in twin-well and triple-well CMOS technologies.