Digital VLSI architectures for beam-enhanced RF aperture arrays

Beam-enhanced digital aperture arrays employ 2-D infinite-impulse-response (IIR) filters as a preprocessing stage for phased/timed-array beamformers to obtain lower side-lobe levels without compromising the array size or the main-lobe selectivity. A digital very-large-scale integration architecture is proposed for beam-enhanced linear aperture arrays. The proposed architecture consists of four subsystems: 2-D IIR prefiltering, beam steering via fast computation of filter coefficients, compensation for nonlinear phase, and phased/timed-array beamforming. Systolic-array architectures are used for first- and second-order 2-D IIR prefiltering subsystems, including fast computation of filter coefficients. The trade-off due to the nonlinear phase response of the 2-D IIR prefilter is partially compensated via fast Fourier transform-based complex phase rotations. Designs are implemented on a Xilinx Virtex-6 XC6VLX240T field-programmable gate-array device and verified using on-chip hardware cosimulation. Field-programmable gate-array designs for both 2-D IIR prefiltering and filter coefficient computation are mapped to standard-cell application-specific integrated circuits in 45 nm complementary metal-oxide semiconductor technology up to the synthesis level with supply VDC = 1.1 V. For a simulation having 64 antennas with binary phase-shift keying modulation, the beam-enhanced aperture array provides better than 10 dB improvement in bit error rate versus signal-to-interference ratio performance compared to phased/timed-array beamforming.