Title :
RTL Synthesis: From Logic Synthesis to Automatic Pipelining
Author :
Cortadella, Jordi ; Galceran-Oms, Marc ; Kishinevsky, Mike ; Sapatnekar, Sachin S.
Author_Institution :
Univ. Polite`cnica de Catalunya, Barcelona, Spain
Abstract :
Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs.
Keywords :
electronic design automation; logic design; pipelines; semiconductor industry; RTL synthesis; automatic pipelining; complex designs; design automation; elastic timing; logic synthesis; semiconductor industry; Design automation; Integrated circuit modeling; Logic gates; Logic synthesis; Optimization; Pipeline processing; Design automation; architectural pipelining; high-level synthesis; logic synthesis; timing elasticity;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/JPROC.2015.2456189
