• DocumentCode
    3607408
  • Title

    Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX

  • Author

    Sahay, Shubham ; Kumar, Mamidala Jagadesh

  • Author_Institution
    Dept. of Electr. Eng., IIT Delhi, Delhi, India
  • Volume
    62
  • Issue
    11
  • fYear
    2015
  • Firstpage
    3882
  • Lastpage
    3886
  • Abstract
    In this brief, we demonstrate using 2-D simulations that the use of a heterodielectric BOX (HDB) above a highly doped ground plane can control the tunneling width at the channel-drain interface and lead to a significant reduction in the ambipolar current in tunnel FETs (TFETs). The HDB consists of SiO2 under the source and the channel regions, and HfO2 under the drain region. When the thickness of the HDB is 25 nm and the ground plane is heavily doped, we show that the drain region at the channel-drain interface is effectively depleted. As a result, the tunneling width at the channel-drain interface increases leading to a complete suppression of ambipolar conduction in a TFET even when the gate voltage VGS = -0.8 V.
  • Keywords
    field effect transistors; hafnium compounds; silicon compounds; tunnel transistors; tunnelling; HDB; HfO2; SiO2; TFET; ambipolar current reduction; channel-drain interface; doped ground plane; drain side tunneling width control; heterodielectric BOX; tunnel field effect transistor; Doping; Electron traps; Field effect transistors; Logic gates; Tunneling; Ambipolarity; ON-state current; source-pocket (p-n-p-n) tunneling FET (TFET); source-pocket (p-n-p-n) tunneling FET (TFET).;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2015.2478955
  • Filename
    7286818