OFF-State Inrush-Current-Induced Electrical Parameter Degradations for High-Voltage Lateral DMOS Transistors

In this paper, the electrical parameter degradations for the n-type lateral double-diffused MOS (nLDMOS) with thin gate oxide and the p-type lateral double-diffused MOS (pLDMOS) with thick gate oxide under the OFF-state inrush current stress have been investigated experimentally. During the stress, although there are the interface states generated at the Si/SiO₂ interface under the polygate terminal for the two devices, the main degradation mechanism for the nLDMOS is positive charges injection into the oxide at that position, while the main one for the pLDMOS is identified to be negative charges trapping into the oxide at that position. In this way, the monitored linear drain current (I_dlin) and the saturation drain current (I_dsat) of the two stressed devices are increased with stressing time due to the induced mirror carriers. Moreover, the differences of depletion layer distributions lead to different current flowing path depths under the above two monitor conditions for the two devices; thereby, the influences upon the electrical parameter degradations from the device damages are also different. In the nLDMOS, the I_dsat flowing path under the polygate terminal is far away from the interface, so that the shift of I_dlin is always much larger than that of I_dsat. In the pLDMOS, the I_dsat flowing path under the polygate terminal is much closer to the surface; as a result, the I_dlin shift is smaller than that of I_dsat.