Improved Off-Current and Modeling in Sub-430 °C Si p-i-n Selector for Unipolar Resistive Random Access Memory

Despite the excellent performance of silicon-based selector devices, high epitaxy temperature (T_epi > 700 °C) is the key constraint for Si selector technology compatibility with back-end-of-the-line (BEOL) process. Recently, we have demonstrated the high performance sub-430 °C epitaxial Si p-i-n selector. In this letter, we identify a two-step mechanism that affects the off-current (IOFF) performance of low temperature epitaxial Si p-i-n diodes using molecular beam epitaxy (MBE). First, the Tepi dependent i-region encroachment by surface dopant segregation shows excellent agreement with the surface diffusion model and demonstrates its validity down to 400 °C. Second, the trap assisted tunneling model is used to evaluate the impact of the modified i-region thickness (due to surface dopant segregation) on IOFF. Improved ideality factor (2×) and IOFF performance (10²×) of sub-430 °C p-i-n diode is related to contamination control-a critical challenge in BEOL processing. Based on the experimentally validated model, we present the IOFF dependence on the i-region thickness. We show that i-region thickness of 50 nm produces sufficiently low leakage, while higher i-region produces marginal IOFF improvement. Thus, the low temperature epitaxial Si p-i-n junction technology is a promising step toward BEOL compatible Si selector technology.