Gate Capacitance Model for Aligned Carbon Nanotube FETs With Arbitrary CNT Spacing

In this paper, we present a gate capacitance model for the aligned carbon nanotube (CNT) array-based FETs with arbitrary distribution of separations between CNTs. By using conformal mapping, the boundary conditions of a capacitor formed by a CNT and a finite planar gate electrode are transformed into a symmetrical circular geometry that simplifies the formulation of the capacitance. The derived model shows improved accuracy compared with the existing models in most of the practical situations, including closely packed CNTs with strong electric field screening, nonuniform CNT spacing, endpoint capacitance with finite gate electrode termination, and substrate material with a different dielectric constant from the gate dielectric. The model has been extensively verified by numerical simulation. To demonstrate the usefulness of the model, it has been applied to predict the gate capacitance of a CNTFET with an experimentally measured CNT spacing distribution.