DocumentCode :
3608863
Title :
A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications
Author :
Johnson, Anju P. ; Chakraborty, Rajat Subhra ; Mukhopadhyay, Debdeep
Author_Institution :
Secured Embedded Architecture Laboratory??(SEAL), Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India
Volume :
1
Issue :
2
fYear :
2015
Firstpage :
110
Lastpage :
122
Abstract :
The Internet of Things (IoT) is a dynamic, ever-evolving “living” entity. Hence, modern Field Programmable Gate Array (FPGA) devices with Dynamic Partial Reconfiguration (DPR) capabilities, which allow in-field non-invasive modifications to the circuit implemented on the FPGA, are an ideal fit. Usually, the activation of DPR capabilities requires the procurement of additional licenses from the FPGA vendor. In this work, we describe how IoTs can take advantage of the DPR capabilities of FPGAs, using a modified DPR methodology that does not require any paid “add-on” utility, to implement a lightweight cryptographic security protocol. We analyze possible threats that can emanate from the availability of DPR at IoT nodes, and propose possible solution techniques based on Physically Unclonable Function (PUF) circuits to prevent such threats.
Keywords :
Computer architecture; Cryptography; Field programmable gate arrays; Partial reconfiguration; Trojan horses; Cryptographic Protocol; Cryptographic protocol; Dynamic Partial Reconfiguration; Field Programmable Gate Arrays; Hardware Trojans; Internet of Things; Physically Unclonable Functions; dynamic partial reconfiguration; field programmable gate arrays; hardware Trojans; physically unclonable functions;
fLanguage :
English
Journal_Title :
Multi-Scale Computing Systems, IEEE Transactions on
Publisher :
ieee
Type :
jour
DOI :
10.1109/TMSCS.2015.2494014
Filename :
7303941
Link To Document :
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