Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time

In this paper a three-stage dynamic-biased CMOS amplifier is designed with a robust optimization of its settling-time performance. The methodology studies the stability of a third order system through the so-called “separation factors” and analyzes the settling time performance through the use of contour plots, in order to define a suitable design strategy. The approach is experimentally validated through the design of a three-stage amplifier with a new compensation network. Monte Carlo simulations as well as experimental results on an integrated prototype demonstrate the validity of the proposed method.