Feasibility Analysis of High-Density Spin-Transfer-Torque Random-Access-Memory With Shared Access Transistor Structure

The spin-transfer-torque random-access-memory (STTRAM) cell size is dominated by access transistors. A shared-access-transistor structure increases the number of bits per cell, but suffers from sneak leakage issues. It is proposed in this letter to use two-terminal selectors to enable this 1-transistor-n-MTJ cell design. Simulation based on reported nonlinear selectors provides the basic proof of feasibility, and identifies key technology requirements to optimize this high-density STTRAM.