Design of a 700 V DB-nLDMOS Based on Substrate Termination Technology

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of ΔL₁, ΔL₂, and ΔL₃ which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low RON,sp of 105.6 mΩ · cm² based on Ld and high BV of 788 V are achieved by the DB-nLDMOS.